S3 Group's clients benefit from a wealth of experience of physical implementation in deep sub-micron processes. We have been delivering designs in 90nm since 2003 and in 65nm since 2004, successfully targeting a variety of foundries with a compelling right-first-time record.
Physical Implementation
At S3 Group we understand how different physical phenomena begin to influence and interact as process geometries continue to shrink. We implement a variety of design and verification strategies to ensure that factors such as yield, manufacturability, gate level effects, signal integrity, static and dynamic power and speed are properly considered and addressed to deliver optimized results.
Clients benefiting from S3 Group's methodology access very accurate results avoiding unnecessary design guard-banding and saving valuable die area and additional spin costs. Our flow covers:
- Placement & Routing
- Physical & Formal Verification
- Signal Integrity (SI) & Crosstalk Testing
- Static Timing Analysis (STA)
- Multiple Supply Voltage (MSV)
- Leakage Current Reduction Techniques
- Clock & Supply Voltage Gating
- Synthesis including Low Power Optimization
- DfT to ensure testability of designs
- DFM to maximize production yields through design
Clients typically engage with S3 Group at the start of the design cycle to ensure that all design hurdles are identified early and planned for appropriately. Clients also benefit from our long established relationships and experience with leading foundries including TSMC, IBM and UMC.
S3 Group has published widely in this area and partners with key technology suppliers such as Cadence.
