RF & Wireless

Publications & White papers

  • Martin Hujer, Radek Maňásek, Jerry O'Mahony, Patrick Feerick, Mark Barry and Brendan Walsh: Wireless Transceiver Modeling Using Verilog-AMS and SystemC, IEEE International Behavioral Modeling and Simulation Conference, San Jose, 2006
    www.bmas-conf.org/2006/5.4_paper.pdf

Abstract:
This paper presents an original methodology for use of Verilog-AMS and SystemC to model a highly integrated wireless transceiver. Novel structures allow the model to be reconfigurable for extensive early architectural analysis and easy re-mapping to new wireless standards and applications. Matlab plots are used to demonstrate the usefulness of the model simulations in the analysis of complex combined digital and analog functionality such as automatic gain control and DC offset correction. Performance results for the simulations as well as development effort are also presented thus showing how this methodology is well suited to the modeling of integrated nanometer wireless transceivers.

Abstract:
In implementing complex mixed signal systems on chip (SoC), in nanometer technology, there needs to be a simulation flow which allows rapid design convergence between the RF, analog & digital parts of the chip. The design teams specializing in these different disciplines need a common simulation environment to verify the integration and architectural partitioning of these parts on the same chip. With high mask costs at this technology node it is essential to mitigate the risk of re-spins as much as possible.
This paper will describe such a flow based on using the Cadence Virtuoso AMS Designer tool. It will outline the common testbench infrastructure built for chip level simulations, give insight on how to model analog/rf blocks for high speed chip level simulation and self-checking connectivity. Examples of analog chip level monitors will also be given.
The lessons learned from the flow implementation will help new and existing users to tailor their simulation environment to efficiently bridge the analog/digital divide, speed up their chip level simulations and optimize their code development.
The flow has been developed and implemented on two recent 90nm mixed signal chips developed by S3 Group. The first has had its silicon verified to be first time connectivity correct while the second has just recently taped out.